1. Field of the Invention
The present invention relates to a data Input/Output (I/O) apparatus for use in a memory device, and more particularly to a data I/O apparatus for use in a memory device, which performs data transmission using the same polarity when neighbor global I/O lines have opposite polarities to reduce coupling noise generated between global I/O lines acting as data I/O lines of a memory device, performs data recovery, and basically deletes the coupling noise, such that it reduces the failure rate of the memory device.
2. Description of the Related Art
With the increasing development of large-capacity DRAMs and high-speed DRAMs, improved DRAMs, each of which includes a sub wordline drive for operating a word line at a high speed and a hierarchical I/O line structure in which Local Input Output (LIO) and Global Input Output (GIO) lines of a data line are configured in the form of a hierarchical structure, have become widely used.
FIG. 1 is a structural diagram illustrating data I/O lines for use in a conventional DRAM including four banks.
Referring to FIG. 1, each of banks 0˜3 include a row controller (X_CTRL) for enabling a word line (WL) and a column selector (Y_CTRL) for enabling a column selection signal (Yi) to determine a cell designated by the enabled word line (WL).
Data lines for reading/writing data of a cell determined by the word line (WL) and the column selection signal (Yi) are called I/O lines.
The above-mentioned I/O lines are differently called a Segment IO (SIO) line, a Local IO (LIO) line, and a Global IO (GIO) line, etc. according to their positions.
Elaborating upon functions of individual IO lines according to read paths, data of a cell bit line is amplified by the column selection signal (Yi) and the amplified data is loaded on a specific IO line. In this case, the specific IO line is indicative of an SIO line.
Thereafter, a data loaded on the SIO line is loaded on an LIO line which shares SIO lines of cell segment blocks classified for every Bit Line Sense Amplifier (BLSA) block of a single bank, such that it is applied to an Input Output Sense Amplifier (IOSA) for each bank.
Data sensed by the IOSA is loaded on the GIO line.
The above-mentioned GIO line acts as a bank-sharing line, and is indicative of a signal line drivable by each of four banks (Bank0˜Bank3).
Data of the GIO line is outputted via desired data pads DQ0, DQ1, DQ2, . . . , DQn-1 by an output driver, such that it can be read.
With the increasing development of high-speed DRAMs and low-power DRAMs, chip size and VDD voltage have become increasingly reduced. Therefore, levels of individual signals are lowered and an interval between lines is also reduced. The reduced VDD voltage and the reduced interval between the lines incur increased parasitic capacitance, and coupling noise between the lines is also increased due to the increased parasitic capacitance, such that the increased coupling noise generates a DRAM failure.
Particularly, a DRAM part greatly affected by the coupling noise is indicative of a GIO line acting as a data I/O line. The GIO line is indicative of the longest line of the DRAM. The higher the frequency, the shorter the line transition time. A specific phenomenon such as coupling noise frequently occurs in the GIO line.
There are a variety of methods for reducing the coupling noise in the above-mentioned GIO line, for example, a method of forming a GIO shield (VSS) line in an interval between GIO lines, and a method of employing a test mode line, etc.
The above-mentioned method for forming the VSS line in the interval between the GIO lines has a disadvantage in that it frequently incurs in the GIO line due to unexpected shaking of the VSS line and thus generally requires an additional repeater. However, the above-mentioned method for forming the VSS line in the interval between the GIO lines is the most popular method in recent times, and has another disadvantage in that it is unable to basically delete the coupling noise.
The above-mentioned method for employing the test mode line is affected by the GIO line, changes a current polarity to another polarity of a test mode, and affects DRAM operations, resulting in DRAM failure.